Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions

In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.