Multiplication With $m$ :2 and $m$ :3 Compressors—A Comparative Review

Compressors are widely used in multipliers to accumulate and reduce partial products in a parallel manner. This paper conducts a comparative review for high-order $m$ :2 and $m$ :3 compressors within a 16-bit $\times16$ -bit multiplier cell as a benchmark. Furthermore, some of the compressors are slightly modified with the aim of reducing interconnections and logical gates. Four well-known adders are also employed to perform the final addition of partial products. They are ripple-carry adder, carry-lookahead adder (CLA), carry-bypass adder, and carry-select adder. These adders are initially demonstrated by a sequence of unmodified identical blocks. Then, they are simplified in order to decrease hardware components. Their simplification and the use of reduced compressors lead to high speed and considerable power and area savings. Synthesizable structural VHDL code is used to simulate and implement different multipliers. Our investigations show that the design with the reduced $m$ :2 compressors and multilevel CLA is the most efficient multiplier. This paper also includes further comparisons with multipliers containing other structures and arrangements.