Six-Side Molded Panel-Level Chip Scale Package with Multiple Diced Wafers

In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.