Sanaz Haddadian;J. Christoph Scheytt;Gerd vom Bögel;Thorben Grenter
{"title":"一种与RFID MIMO读卡器技术兼容的亚阈值微波RFID标签芯片","authors":"Sanaz Haddadian;J. Christoph Scheytt;Gerd vom Bögel;Thorben Grenter","doi":"10.1109/JRFID.2023.3308332","DOIUrl":null,"url":null,"abstract":"We present a fully integrated radio frequency identifications transponder chip operating at 5.8 GHz, which is compatible with the class-1 generation-2 of the Electronic Product Code protocol (EPC-C1 G2). The tag chip including the analog front-end and the digital baseband processor, are designed in the sub-threshold regime (0.5 V) with a total supply current of less than <inline-formula> <tex-math notation=\"LaTeX\">$50~\\mu \\text{A}$ </tex-math></inline-formula>. As a power scavenging unit, a single-stage differential-drive rectifier structure is designed and fabricated with standard threshold voltage (SVT) MOS elements in a commercial 65-nm CMOS process, to provide 0.8 V of rectified voltage. Measurements performed on the fabricated single-stage structure show a maximum power conversion efficiency of 69.6% for a 22 <inline-formula> <tex-math notation=\"LaTeX\">$\\text{k}\\Omega $ </tex-math></inline-formula> load and a sensitivity of −12.5 dBm, which corresponds to more than 1 m of reading range. The power conversion efficiency at this range is about 64%.","PeriodicalId":73291,"journal":{"name":"IEEE journal of radio frequency identification","volume":"7 ","pages":"556-563"},"PeriodicalIF":2.3000,"publicationDate":"2023-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/7433271/10004382/10233935.pdf","citationCount":"0","resultStr":"{\"title\":\"A Sub-Threshold Microwave RFID Tag Chip, Compatible With RFID MIMO Reader Technology\",\"authors\":\"Sanaz Haddadian;J. Christoph Scheytt;Gerd vom Bögel;Thorben Grenter\",\"doi\":\"10.1109/JRFID.2023.3308332\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a fully integrated radio frequency identifications transponder chip operating at 5.8 GHz, which is compatible with the class-1 generation-2 of the Electronic Product Code protocol (EPC-C1 G2). The tag chip including the analog front-end and the digital baseband processor, are designed in the sub-threshold regime (0.5 V) with a total supply current of less than <inline-formula> <tex-math notation=\\\"LaTeX\\\">$50~\\\\mu \\\\text{A}$ </tex-math></inline-formula>. As a power scavenging unit, a single-stage differential-drive rectifier structure is designed and fabricated with standard threshold voltage (SVT) MOS elements in a commercial 65-nm CMOS process, to provide 0.8 V of rectified voltage. Measurements performed on the fabricated single-stage structure show a maximum power conversion efficiency of 69.6% for a 22 <inline-formula> <tex-math notation=\\\"LaTeX\\\">$\\\\text{k}\\\\Omega $ </tex-math></inline-formula> load and a sensitivity of −12.5 dBm, which corresponds to more than 1 m of reading range. The power conversion efficiency at this range is about 64%.\",\"PeriodicalId\":73291,\"journal\":{\"name\":\"IEEE journal of radio frequency identification\",\"volume\":\"7 \",\"pages\":\"556-563\"},\"PeriodicalIF\":2.3000,\"publicationDate\":\"2023-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/iel7/7433271/10004382/10233935.pdf\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE journal of radio frequency identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10233935/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE journal of radio frequency identification","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10233935/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Sub-Threshold Microwave RFID Tag Chip, Compatible With RFID MIMO Reader Technology
We present a fully integrated radio frequency identifications transponder chip operating at 5.8 GHz, which is compatible with the class-1 generation-2 of the Electronic Product Code protocol (EPC-C1 G2). The tag chip including the analog front-end and the digital baseband processor, are designed in the sub-threshold regime (0.5 V) with a total supply current of less than $50~\mu \text{A}$ . As a power scavenging unit, a single-stage differential-drive rectifier structure is designed and fabricated with standard threshold voltage (SVT) MOS elements in a commercial 65-nm CMOS process, to provide 0.8 V of rectified voltage. Measurements performed on the fabricated single-stage structure show a maximum power conversion efficiency of 69.6% for a 22 $\text{k}\Omega $ load and a sensitivity of −12.5 dBm, which corresponds to more than 1 m of reading range. The power conversion efficiency at this range is about 64%.