容错混合临界系统的峰值功率感知全寿命可靠性改进

IF 2.4 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE open journal of circuits and systems Pub Date : 2022-09-20 DOI:10.1109/OJCAS.2022.3207598
Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar
{"title":"容错混合临界系统的峰值功率感知全寿命可靠性改进","authors":"Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar","doi":"10.1109/OJCAS.2022.3207598","DOIUrl":null,"url":null,"abstract":"Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named \n<inline-formula> <tex-math>${\\mathbf {L}}ife-time \\,\\,{\\mathbf {P}}eak \\,\\,{\\mathbf {P}}{ower~management~in}\\,\\,{\\mathbf {M}}{ixed}-{\\mathbf {C}}{riticality\\,\\, systems}$ </tex-math></inline-formula>\n (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4000,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896164","citationCount":"2","resultStr":"{\"title\":\"Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems\",\"authors\":\"Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar\",\"doi\":\"10.1109/OJCAS.2022.3207598\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named \\n<inline-formula> <tex-math>${\\\\mathbf {L}}ife-time \\\\,\\\\,{\\\\mathbf {P}}eak \\\\,\\\\,{\\\\mathbf {P}}{ower~management~in}\\\\,\\\\,{\\\\mathbf {M}}{ixed}-{\\\\mathbf {C}}{riticality\\\\,\\\\, systems}$ </tex-math></inline-formula>\\n (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.\",\"PeriodicalId\":93442,\"journal\":{\"name\":\"IEEE open journal of circuits and systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.4000,\"publicationDate\":\"2022-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896164\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE open journal of circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/9896164/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE open journal of circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/9896164/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 2

摘要

混合临界系统(mcs)包括具有多个临界级别和不同运行模式的任务。这些系统在保证安全运行的同时,带来了节能、节约资源等效益。然而,管理可用资源以实现高利用率、低功耗和所需的可靠性水平对mcs来说是一个挑战。在许多情况下,这两个目标之间存在权衡。例如,尽管使用容错技术(如复制)可以提高定时可靠性,但它会增加功耗,并可能威胁到生命周期的可靠性。在这项工作中,我们引入了一种名为${\mathbf {L}} life -time \,\,{\mathbf {P}}eak \,\,{\mathbf {P}}{power ~management~ In}\,\,{\mathbf {M}}{ixed}-{\mathbf {C}}{criticality \,\, systems}$ (LPP-MC)的方法来保证可靠性,同时降低峰值功率。这种方法使用一种称为可靠性-功率度量(RPM)的新度量来映射任务。LPP-MC方法使用这个指标来平衡不同处理器内核的功耗,并提高芯片的使用寿命。此外,为了保证mcs的定时可靠性,该方法还采用了任务重执行的容错技术。我们通过一个真实的航电任务集和各种合成任务集来评估所提出的方法。实验结果表明,与现有方法相比,该方法可降低老化率20.6%,峰值功率降低17.6%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems
Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named ${\mathbf {L}}ife-time \,\,{\mathbf {P}}eak \,\,{\mathbf {P}}{ower~management~in}\,\,{\mathbf {M}}{ixed}-{\mathbf {C}}{riticality\,\, systems}$ (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
审稿时长
19 weeks
期刊最新文献
Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1