Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins
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A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC
A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.
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