6b 3GS/s 11mW全动态闪存ADC, 40nm CMOS，减少了比较器的数量

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243772

Yun-Shiang Shu

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引用次数: 92

摘要

6b 3GS/s全动态闪存ADC是在40nm CMOS上制造的，占地0.021mm2。采用不平衡尾实现了内置偏置数字控制的动态比较器。一半的比较器用简单的SR锁存器代替。该ADC在直流和奈奎斯特电压下的信噪比分别为36.2dB和33.1dB，功耗为11mW，电源电压为1.1V。

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A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators

A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021mm2. Dynamic comparators with digitally controlled built-in offset are realized with imbalanced tails. Half of the comparators are substituted with simple SR latches. The ADC achieves SNDRs of 36.2dB and 33.1dB at DC and Nyquist, respectively, while consuming 11mW from a 1.1V supply.

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2012 Symposium on VLSI Circuits (VLSIC)

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