Al2O3栅极介质下d模AlGaN/GaN mishemt的阈值电压不稳定性

Ye Liang, Yuanlei Zhang, Yutao Cai, Zhaoyi Wang, Yinchao Zhao, H. Wen, Wen Liu
{"title":"Al2O3栅极介质下d模AlGaN/GaN mishemt的阈值电压不稳定性","authors":"Ye Liang, Yuanlei Zhang, Yutao Cai, Zhaoyi Wang, Yinchao Zhao, H. Wen, Wen Liu","doi":"10.1109/ICICDT51558.2021.9626513","DOIUrl":null,"url":null,"abstract":"In this paper, D-mode MIS-HEMTs with 24 nm ALD-Al2O3 gate dielectric are studied. The electrical parameters, such as threshold voltage (Vth), drain current (Ids), on-resistant (Ron), sub-threshold swing (SS), and gate leakage current (Ileak) are investigated during the gate stress phase and recovery phase at room temperature. It is found that, during the stress phase, Vth and Ron show positive shifts while Ids show negative shifts. It is because channel electrons are trapped by the dielectric/III-nitride interface layer and by the bulk traps in the gate dielectric. However, these electrical parameter changes cannot be fully recoverable at the end of the recovery phase, followed by 30 mins thermal de-trapping. It may be caused by (1) positive gate bias induced unrecoverable defects in the dielectric layer. (2) bulk trap has a relatively large emission constant. (3) AlGaN barrier exists between the channel and dielectric/III-nitride interface layer, make the electrons hard to exchanges.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Threshold Voltage Instability in D-mode AlGaN/GaN MIS-HEMTs with Al2O3 Gate Dielectric\",\"authors\":\"Ye Liang, Yuanlei Zhang, Yutao Cai, Zhaoyi Wang, Yinchao Zhao, H. Wen, Wen Liu\",\"doi\":\"10.1109/ICICDT51558.2021.9626513\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, D-mode MIS-HEMTs with 24 nm ALD-Al2O3 gate dielectric are studied. The electrical parameters, such as threshold voltage (Vth), drain current (Ids), on-resistant (Ron), sub-threshold swing (SS), and gate leakage current (Ileak) are investigated during the gate stress phase and recovery phase at room temperature. It is found that, during the stress phase, Vth and Ron show positive shifts while Ids show negative shifts. It is because channel electrons are trapped by the dielectric/III-nitride interface layer and by the bulk traps in the gate dielectric. However, these electrical parameter changes cannot be fully recoverable at the end of the recovery phase, followed by 30 mins thermal de-trapping. It may be caused by (1) positive gate bias induced unrecoverable defects in the dielectric layer. (2) bulk trap has a relatively large emission constant. (3) AlGaN barrier exists between the channel and dielectric/III-nitride interface layer, make the electrons hard to exchanges.\",\"PeriodicalId\":6737,\"journal\":{\"name\":\"2021 International Conference on IC Design and Technology (ICICDT)\",\"volume\":\"13 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Conference on IC Design and Technology (ICICDT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT51558.2021.9626513\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on IC Design and Technology (ICICDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT51558.2021.9626513","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

本文研究了24 nm ALD-Al2O3栅极介质的d模miss - hemt。研究了室温下栅应力阶段和恢复阶段的阈值电压(Vth)、漏极电流(Ids)、导通电阻(Ron)、亚阈值摆幅(SS)和栅漏电流(Ileak)等电学参数。结果表明,在应力阶段,Vth和Ron为正位移,而id为负位移。这是因为通道电子被介电/ iii -氮化物界面层和栅极介电中的体阱捕获。然而,这些电气参数的变化不能在回收阶段结束时完全恢复,随后是30分钟的热脱陷。它可能是由(1)正栅极偏压引起的介电层中不可恢复的缺陷引起的。(2)散装疏水阀具有较大的发射常数。(3)通道与介质/ iii -氮化物界面层之间存在AlGaN势垒,使得电子难以交换。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Threshold Voltage Instability in D-mode AlGaN/GaN MIS-HEMTs with Al2O3 Gate Dielectric
In this paper, D-mode MIS-HEMTs with 24 nm ALD-Al2O3 gate dielectric are studied. The electrical parameters, such as threshold voltage (Vth), drain current (Ids), on-resistant (Ron), sub-threshold swing (SS), and gate leakage current (Ileak) are investigated during the gate stress phase and recovery phase at room temperature. It is found that, during the stress phase, Vth and Ron show positive shifts while Ids show negative shifts. It is because channel electrons are trapped by the dielectric/III-nitride interface layer and by the bulk traps in the gate dielectric. However, these electrical parameter changes cannot be fully recoverable at the end of the recovery phase, followed by 30 mins thermal de-trapping. It may be caused by (1) positive gate bias induced unrecoverable defects in the dielectric layer. (2) bulk trap has a relatively large emission constant. (3) AlGaN barrier exists between the channel and dielectric/III-nitride interface layer, make the electrons hard to exchanges.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control Design process interactions in shallow trench isolation chemical mechanical planarization for layout diversification and design optimization Approaches for Optimizing Near Infrared Si Photodetectors Based on Internal Photoemission Deterministic Tagging Technology for Device Authentication Robust Training of Optical Neural Network with Practical Errors using Genetic Algorithm: A Case Study in Silicon-on-Insulator-Based Photonic Integrated Chips
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1