2.5- 3.3 ghz CMOS d类压控振荡器

Luca Fanori, P. Andreani
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引用次数: 37

摘要

用于无线通信的LC振荡器的功耗是一个热门的研究课题,其中c类振荡器已被提出以提高标准b类振荡器(通常称为交叉耦合差分对LC-tank振荡器)的效率。在这项工作中,我们引入了d类振荡器,以进一步降低功耗,达到所需的相位噪声水平。d类振荡器早在1959年就被发现了,但它们在GHz应用中的应用必须等待nm CMOS工艺提供具有可控寄生电容的优秀开关。该VCO采用标准的65nm CMOS工艺设计,没有任何厚金属层。LC槽采用单匝四指0.59nH电感器,在3GHz时的Q值为10-11,从布局后仿真(包括PCB)拟合测量的功耗估计。
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A 2.5-to-3.3GHz CMOS Class-D VCO
Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator has been proposed to improve the efficiency of the standard Class-B oscillator (most often referred to as cross-coupled differential-pair LC-tank oscillator). In this work, we introduce the Class-D oscillator to further reduce power consumption for a desired phase noise level. Class-D oscillators have been known since 1959, but their use in GHz applications had to wait for nm CMOS processes offering excellent switches with manageable parasitic capacitances. The VCO has been designed in a standard 65nm CMOS process without any thick metal layer. The LC tank, employing a single-turn four-finger 0.59nH inductor, has a Q of 10-11 at 3GHz, estimated from post-layout simulations (including PCB) fitting the measured power consumption.
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