{"title":"1 GHz时钟操作的约瑟夫森RAMs","authors":"Shuichi Nagasawa, Hideaki Numata, Yoshihito Hashimoto, Shuichi Tahara","doi":"10.1016/S0964-1807(98)00113-6","DOIUrl":null,"url":null,"abstract":"<div><p><span>A Josephson 256 word×16 bit RAM that includes a power circuit has been designed to enable high-frequency clock operation. This RAM consists of a 4×4 matrix array of 256 RAM blocks, impedance matching lines, and input signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned properly at a high clock frequency of 1 GHz with less than 3 mW of </span>power dissipation<span> from an external power source.</span></p></div>","PeriodicalId":100110,"journal":{"name":"Applied Superconductivity","volume":"6 7","pages":"Pages 445-451"},"PeriodicalIF":0.0000,"publicationDate":"1998-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S0964-1807(98)00113-6","citationCount":"1","resultStr":"{\"title\":\"1 GHz clock operation of Josephson RAMs\",\"authors\":\"Shuichi Nagasawa, Hideaki Numata, Yoshihito Hashimoto, Shuichi Tahara\",\"doi\":\"10.1016/S0964-1807(98)00113-6\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p><span>A Josephson 256 word×16 bit RAM that includes a power circuit has been designed to enable high-frequency clock operation. This RAM consists of a 4×4 matrix array of 256 RAM blocks, impedance matching lines, and input signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned properly at a high clock frequency of 1 GHz with less than 3 mW of </span>power dissipation<span> from an external power source.</span></p></div>\",\"PeriodicalId\":100110,\"journal\":{\"name\":\"Applied Superconductivity\",\"volume\":\"6 7\",\"pages\":\"Pages 445-451\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/S0964-1807(98)00113-6\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Applied Superconductivity\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0964180798001136\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Applied Superconductivity","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0964180798001136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Josephson 256 word×16 bit RAM that includes a power circuit has been designed to enable high-frequency clock operation. This RAM consists of a 4×4 matrix array of 256 RAM blocks, impedance matching lines, and input signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned properly at a high clock frequency of 1 GHz with less than 3 mW of power dissipation from an external power source.
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