O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout
{"title":"基于面积释放能量的新型铜低钾键垫结构损伤灵敏度分析","authors":"O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout","doi":"10.1109/ESIME.2006.1644041","DOIUrl":null,"url":null,"abstract":"This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"190 1","pages":"1-8"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy\",\"authors\":\"O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout\",\"doi\":\"10.1109/ESIME.2006.1644041\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken\",\"PeriodicalId\":60796,\"journal\":{\"name\":\"微纳电子与智能制造\",\"volume\":\"190 1\",\"pages\":\"1-8\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"微纳电子与智能制造\",\"FirstCategoryId\":\"1087\",\"ListUrlMain\":\"https://doi.org/10.1109/ESIME.2006.1644041\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"微纳电子与智能制造","FirstCategoryId":"1087","ListUrlMain":"https://doi.org/10.1109/ESIME.2006.1644041","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy
This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken