Optimizing X-Ray Inspection for Advanced Packaging Applications

Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said the same in the 60’s. But after decades of increased device level integration, it is an important change. Figure 1 shows an example (future) device: there are large bumps, hybrid bonds--for extreme bandwidth and low latency connection to cache memory, TSV based DRAM, and multiple CPU to CPU interconnects. Each of these is a failure point. Figure 1: The wide variety of interconnects on future advanced packages Figure 2: the triangle of misery as applied to standard and Advanced xray imaging (AXI) Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.