T. Morie, Haichao Liang, Takashi Tohara, Hirofumi Tanaka, M. Igarashi, S. Samukawa, K. Endo, Yasuo Takahashi
{"title":"低功耗下纳米器件的时域加权和计算","authors":"T. Morie, Haichao Liang, Takashi Tohara, Hirofumi Tanaka, M. Igarashi, S. Samukawa, K. Endo, Yasuo Takahashi","doi":"10.1109/NANO.2016.7751490","DOIUrl":null,"url":null,"abstract":"This paper introduces a time-domain weighted-sum calculation operation based on a spiking neuron model, and discusses a resistance-capacitance circuit that performs a calculation operation assumed to be realized in CMOS VLSI technology. A nanodevice that executes this calculation is also presented. The calculation circuit is useful for extremely low power operation. This operation uses the rising slopes of post-synaptic potentials triggered by input spike pulses. In the time-domain calculation circuit, the energy dissipation is independent of the resistance, and only depends on the capacitance and voltages. However, the time constant, which is the product of the resistance and capacitance, should be relatively large to guarantee the calculation resolution, and therefore the resistance should be at the giga-ohms levels. The nanodevice consists of a nanodisk array connected with a fin field-effect transistor. Nanodisk arrays can be fabricated using a self-assembly bio-nano-template technique, and they act as resistors with resistance levels of several giga-ohms. A weighted sum can be achieved with an energy dissipation on the order of 1 fJ, with a number of inputs that can be more than 100. This amount of energy is several orders of magnitude lower than that of conventional digital processors.","PeriodicalId":6646,"journal":{"name":"2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)","volume":"23 1","pages":"390-392"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Spike-based time-domain weighted-sum calculation using nanodevices for low power operation\",\"authors\":\"T. Morie, Haichao Liang, Takashi Tohara, Hirofumi Tanaka, M. Igarashi, S. Samukawa, K. Endo, Yasuo Takahashi\",\"doi\":\"10.1109/NANO.2016.7751490\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a time-domain weighted-sum calculation operation based on a spiking neuron model, and discusses a resistance-capacitance circuit that performs a calculation operation assumed to be realized in CMOS VLSI technology. A nanodevice that executes this calculation is also presented. The calculation circuit is useful for extremely low power operation. This operation uses the rising slopes of post-synaptic potentials triggered by input spike pulses. In the time-domain calculation circuit, the energy dissipation is independent of the resistance, and only depends on the capacitance and voltages. However, the time constant, which is the product of the resistance and capacitance, should be relatively large to guarantee the calculation resolution, and therefore the resistance should be at the giga-ohms levels. The nanodevice consists of a nanodisk array connected with a fin field-effect transistor. Nanodisk arrays can be fabricated using a self-assembly bio-nano-template technique, and they act as resistors with resistance levels of several giga-ohms. A weighted sum can be achieved with an energy dissipation on the order of 1 fJ, with a number of inputs that can be more than 100. This amount of energy is several orders of magnitude lower than that of conventional digital processors.\",\"PeriodicalId\":6646,\"journal\":{\"name\":\"2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)\",\"volume\":\"23 1\",\"pages\":\"390-392\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NANO.2016.7751490\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2016.7751490","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Spike-based time-domain weighted-sum calculation using nanodevices for low power operation
This paper introduces a time-domain weighted-sum calculation operation based on a spiking neuron model, and discusses a resistance-capacitance circuit that performs a calculation operation assumed to be realized in CMOS VLSI technology. A nanodevice that executes this calculation is also presented. The calculation circuit is useful for extremely low power operation. This operation uses the rising slopes of post-synaptic potentials triggered by input spike pulses. In the time-domain calculation circuit, the energy dissipation is independent of the resistance, and only depends on the capacitance and voltages. However, the time constant, which is the product of the resistance and capacitance, should be relatively large to guarantee the calculation resolution, and therefore the resistance should be at the giga-ohms levels. The nanodevice consists of a nanodisk array connected with a fin field-effect transistor. Nanodisk arrays can be fabricated using a self-assembly bio-nano-template technique, and they act as resistors with resistance levels of several giga-ohms. A weighted sum can be achieved with an energy dissipation on the order of 1 fJ, with a number of inputs that can be more than 100. This amount of energy is several orders of magnitude lower than that of conventional digital processors.