{"title":"第19部分概述:频率生成","authors":"A. Mazzanti, Xiang Gao, P. Wambacq","doi":"10.1109/ISSCC.2017.7870390","DOIUrl":null,"url":null,"abstract":"This session covers the latest advancements in frequency sources and synthesis, fundamental blocks for communication, sensing and imaging systems. The first presentation in the session demonstrates a high-efficiency, high-power multiport radiating element at 114GHz in a SiGe BiCMOS technology. The second paper proposes an efficient calibration technique applied to a 27-to-31GHz injection-locking frequency multiplier with quadrature outputs. The next three presentations discuss frequency synthesizers. The first is a digital 50-to-66GHz PLL featuring low noise and low spur levels by leveraging a high-speed TDC and intensive calibrations. The second and third PLLs are based on ring-oscillators and leverage subsampling phase detection and FIR filtering, respectively, to achieve simultaneously low noise and compact area. The session is concluded with an ultra-low-voltage DCO in a 16nm FinFET technology.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"36 1","pages":"320-321"},"PeriodicalIF":0.0000,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Session 19 overview: Frequency generation\",\"authors\":\"A. Mazzanti, Xiang Gao, P. Wambacq\",\"doi\":\"10.1109/ISSCC.2017.7870390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This session covers the latest advancements in frequency sources and synthesis, fundamental blocks for communication, sensing and imaging systems. The first presentation in the session demonstrates a high-efficiency, high-power multiport radiating element at 114GHz in a SiGe BiCMOS technology. The second paper proposes an efficient calibration technique applied to a 27-to-31GHz injection-locking frequency multiplier with quadrature outputs. The next three presentations discuss frequency synthesizers. The first is a digital 50-to-66GHz PLL featuring low noise and low spur levels by leveraging a high-speed TDC and intensive calibrations. The second and third PLLs are based on ring-oscillators and leverage subsampling phase detection and FIR filtering, respectively, to achieve simultaneously low noise and compact area. The session is concluded with an ultra-low-voltage DCO in a 16nm FinFET technology.\",\"PeriodicalId\":6511,\"journal\":{\"name\":\"2016 IEEE International Solid-State Circuits Conference (ISSCC)\",\"volume\":\"36 1\",\"pages\":\"320-321\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Solid-State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2017.7870390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2017.7870390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This session covers the latest advancements in frequency sources and synthesis, fundamental blocks for communication, sensing and imaging systems. The first presentation in the session demonstrates a high-efficiency, high-power multiport radiating element at 114GHz in a SiGe BiCMOS technology. The second paper proposes an efficient calibration technique applied to a 27-to-31GHz injection-locking frequency multiplier with quadrature outputs. The next three presentations discuss frequency synthesizers. The first is a digital 50-to-66GHz PLL featuring low noise and low spur levels by leveraging a high-speed TDC and intensive calibrations. The second and third PLLs are based on ring-oscillators and leverage subsampling phase detection and FIR filtering, respectively, to achieve simultaneously low noise and compact area. The session is concluded with an ultra-low-voltage DCO in a 16nm FinFET technology.