基于时钟转发的100+米12Gb/s/lane铜缆链路

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243813

Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang

{"title":"基于时钟转发的100+米12Gb/s/lane铜缆链路","authors":"Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang","doi":"10.1109/VLSIC.2012.6243813","DOIUrl":null,"url":null,"abstract":"This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"122 1","pages":"108-109"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding\",\"authors\":\"Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang\",\"doi\":\"10.1109/VLSIC.2012.6243813\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"122 1\",\"pages\":\"108-109\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243813\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种用于12Gbps 100+米铜缆的时钟转发链路架构。通过FIR滤波技术、低抖动可配置PLL/MDLL和正确选择转发频率，可以沿整个电缆传输低抖动正向时钟。电缆末端的总抖动为4.4ps RMS。数据信号每8m重复一次。在65nm技术中，每个中继器的链路占用0.095mm2的面积，功耗为48mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding

This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2012 Symposium on VLSI Circuits (VLSIC)

自引率

0.00%

发文量