降低铜柱倒装故障率的研究

B. Rosario, J. Holyoak, Mohsen Haji-Rahim, Gene Lambird, Y. Wang, Kendra Lyons, T. Johnson, P. Makowenskyj, Brian T. Myers, S. Pan
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引用次数: 0

摘要

铜柱倒装芯片技术已被证明是可靠的,并广泛应用于芯片到封装的移动模块产品。曾经有一段时间,客户认为500ppm(百万分之一)是可接受的缺陷率。现在,一级客户期望缺陷率低于50ppm。客户的高期望推动了我们的深入研究和问题解决。我们的主要工作包括:1)初始缺陷的映射和分析。2)开发一种检测低缺陷率的有效方法。3)三维力学建模,侧重于多种失效界面和模式。4)模拟应力因子及其影响。5)通过实验装配设计(DOE)验证假设,最终提高成品率。
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Study to Lower Cu Pillar Flip-Chip Failure Rate
Cu pillar flip-chip die technology has proved reliable and is widely used in chip-to-package mobile module products. There was a time when customers considered 500ppm (Parts per million) an acceptable defect rate. Now, tier 1 customers expect a defect rate of less than 50ppm. This high customer expectation drove this in-depth research and problem solve. Our main work includes: 1) Mapping and analyzing initial defects. 2) Developing an effective way to detect a low defect rate. 3) 3D mechanical modeling that focuses on multiple failure interfaces and modes. 4) Simulating stress factors and their impacts. 5) Verifying hypothesis with assembly design of experiment (DOE) and ultimately improved yield.
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