Statistical Wear-Leveling for Phase Change Memory

Wear leveling techniques have been successfully used in increasing the useful life of NAND flash devices. Although Phase-change Memory's endurance is much higher than NAND, and can reach up to a range from 106 to 109, it still lacks the endurance needed for use as system main memory such as DRAM, which has nearly ~1014 rewrite endurance. In this paper, we propose and have developed a novel statistical and hierarchical wear-leveling technique to be used in a 4Gb DRAM-like PCM chip. The technique uses real-time memory address statistics to compute the physical-to-device address mapping using an embedded CPU. The CPU automatically adjust for different system workloads based on current address statistics. Results from system simulations shows the techniques to be effective in our tile-based memory architecture while requiring relatively low computational overhead.