1.5GHz 1.35mW - 112dBc/Hz带内噪声数字锁相环，电源噪声灵敏度为50fs/mV

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243853

A. Elshazly, Rajesh Inti, Mrunmay Talegaonkar, P. Hanumolu

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引用次数: 8

摘要

高度数字化的锁相环采用1b TDC和低功率稳压器来减少大量电源噪声存在时的输出抖动。基于环形振荡器的DPLL采用0.13μm CMOS工艺制造，在1.5GHz输出频率下消耗1.35mW，最坏情况下噪声灵敏度优于50fs/mV(≡噪声为200mVpp，抖动衰减为10pspp)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10pspp jitter degradation with 200mVpp noise).

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2012 Symposium on VLSI Circuits (VLSIC)

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