Breakthroughs in chip embedding technologies leading to the emergence of further miniaturised system-in-packages

allows a very high degree of miniaturization by stacking multiple layers of embedded thin components. This paper shows the realisation of embedded chip QFN-packages (Quad Flat No-Lead) with a size of 10mmx10mm which were manufactured at prototype level at 10„x14„ panels. The embedded chip in the package has a pad pitch of 100µm and the resultant QFN package has a total number of 84I/Os at 400µm footprint pitch. State-of-the-art developments in semi-additive processes by employment of laserdirect- imaging technology (LDI) have demonstrated very fine 18µm lines with 10µm space between them for the final package copper routing. The work in this paper provides evidence for chip embedding capability at very fine chip pad pitch of 100µm and discusses the technology limits. The present work at research prototype level frames the main activities in the EU-Hermes project towards the industrialisation of chip embedding technologies.