高速封装中DDR接口的保护走线和接地过孔分析

2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference Pub Date : 2009-10-01 DOI:10.1109/IMPACT.2009.5382159

R. Sung, K. Chiang, J. Lai, Yu-Po Wang

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摘要

由于需求的小型化，布局设计的面积越来越小。但是，越来越多的函数被集成。在这种情况下，高速设计(如DDR接入接口)容易产生SSN (Simultaneous Switching noise)。本文对该设计进行了分析评价。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Guarding trace and ground via-hole analysis for DDR interface designed in high-speed packages

Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause Simultaneous Switching Noises (SSN). In this paper, some analysis on this design was evaluated.

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2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference

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