Application of TEXTIO in the Simulation of FPGA Image Processing Algorithm

In order to carry out high speed and effective digital image processing, the use of FPGA is a relatively reasonable choice due to the large amount of data in digital image. Thus we need a careful simulation test to verify the correctness of the VHDL code to achieve the corresponding algorithm. It is difficult to achieve the digital image processing algorithm simulation if we rely on the traditional input waveform method. And if we write a test file (Testbench) to generate a number of test vectors, it would be very low efficiency for the simulation test. If we put the real digital image data into a file as test input, not only can the correctness of the algorithm is verified, but also the processed data can be written into the image file. Thus the result can be viewed through image in this directly way which gives us great convenience for designing and debugging. The TEXTIO package of VHDL language provides exactly the function of interaction with the disk file. So we can use it to achieve the digital image processing algorithm simulation. This paper uses the algorithm of image banalization as an example to introduce this method.