使用垂直/水平耦合谐振器的3D时钟分布

Yasuhiro Take, N. Miura, H. Ishikuro, T. Kuroda
{"title":"使用垂直/水平耦合谐振器的3D时钟分布","authors":"Yasuhiro Take, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ISSCC.2013.6487725","DOIUrl":null,"url":null,"abstract":"Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"1 1","pages":"258-259"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"3D clock distribution using vertically/horizontally-coupled resonators\",\"authors\":\"Yasuhiro Take, N. Miura, H. Ishikuro, T. Kuroda\",\"doi\":\"10.1109/ISSCC.2013.6487725\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.\",\"PeriodicalId\":6378,\"journal\":{\"name\":\"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"258-259\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-03-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2013.6487725\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2013.6487725","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

摘要

对于高性能微处理器来说,具有低倾斜、低抖动和低功耗的时钟分布是一个重大的设计挑战。虽然传统的h树时钟分布电路被广泛使用,但这种电路的时钟偏度会因器件缩放引起的PVT变化而增加[1]。近年来,人们对减少时钟偏差的谐振时钟分配方案越来越感兴趣。特别是,与LC谐振器[3]相比,具有短输出的耦合环形振荡器[2]可以减少倾斜和抖动,而无需额外的布局面积。每个振荡器的相位和频率的差异(由于PVT的变化)由振荡器之间的相互连接来平衡。功耗也可以降低,因为增强的可变性容限可能允许在较低的电压下工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
3D clock distribution using vertically/horizontally-coupled resonators
Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A CMOS dual-switching power-supply modulator with 8% efficiency improvement for 20MHz LTE Envelope Tracking RF power amplifiers A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS A fully intraocular 0.0169mm2/pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1