Design and testing of data-driven self-timed RSFQ shift register

We report design, implementation and testing of a superconductive rapid single flux quantum (RSFQ) shift register based on a data-driven self-timed (DDST) architecture, and demonstrated the validity of this asynchronous design approach. In the DDST architecture, a clock signal is localized within the basic modules, and complementary data signals are used between the modules to transmit timing information. A larger system is simply an array of the basic modules and no extra timing consideration is required. Monte Carlo analysis on a 4-bit DDST shift register has shown that a 40-kbit shift register operating at 20 GHz can be built by using the present Nb Josephson technology. We have observed fully correct operation of a cascade of two 4-bit DDST shift registers with dc bias voltage margin of ±15% at low frequency and ±10% at 20 GHz.