采用电荷泵的71dB动态范围三阶ΔΣ TDC

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243843

M. Gande, N. Maghari, Taehwan Oh, U. Moon

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引用次数: 38

摘要

提出了一种高分辨率时数转换器(TDC)结构。该架构结合了噪声整形量化和电荷泵的原理，构建了一个带有专用反馈DAC的三阶ΔΣ TDC。该原型TDC采用0.13μm CMOS工艺，在2.81MHz的信号带宽(OSR=16)下实现了71dB DR和67dB SNDR，功耗为2.58mW。

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A 71dB dynamic range third-order ΔΣ TDC using charge-pump

A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.

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2012 Symposium on VLSI Circuits (VLSIC)

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