在0.13µm BiCMOS中实现四路25Gb/s 270mW TIA,串扰损耗<0.15dB

G. Kalogerakis, T. Moran, Thelinh Nguyen, Gilles Denoyer
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引用次数: 27

摘要

为了降低收发器的成本、复杂性和尺寸,对100Gb/s及以上光传输的推动需要更高速度和集成度的电子元件[1-2]。这需要并行多通道光收发器,每个光收发器的工作速度为25Gb/s或更高。由于发射器输出功率的变化以及在某些情况下不同的光路,并行接收器必须在不同的输入光功率水平下工作。这种趋势增加了集成多通道接收器中可接受的通道间串扰的压力[3]。在超高吞吐量光链路中,当所有信道都运行时,最小化这种串扰损失变得越来越重要。
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A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty
The push for 100Gb/s optical transport and beyond necessitates electronic components at higher speed and integration level in order to drive down cost, complexity and size of transceivers [1-2]. This requires parallel multi-channel optical transceivers each operating at 25Gb/s and beyond. Due to variations in the output power of transmitters and in some cases different optical paths the parallel receivers have to operate at different input optical power levels. This trend places increasing strain to the acceptable inter-channel crosstalk in integrated multi-channel receivers [3]. Minimizing this cross-talk penalty when all channels are operational is becoming increasingly important in ultra-high throughput optical links.
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