一种在FINFET架构内优化的高通量PMOS源漏工艺，适用于大批量芯片制造

2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2020-08-01 DOI:10.1109/ASMC49169.2020.9185252

R. Mahadevapuram, V. Kaushal, A. Raviswaran

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引用次数: 1

摘要

在FINFET结构上开发了一种新型多层eSiGe薄膜，通过优化晶圆内(WiW)均匀性和硼浓度来提高PMOS性能。新工艺减少了大型模具产品中与生长相关的缺陷问题和过量的异常生长缺陷，从而提高了最新半导体芯片的良率和可靠性。

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A high throughput PMOS Source-Drain process optimized within FINFET architecture for high volume chip manufacturing

Developed a novel multi-layered eSiGe film on FINFET architecture to increase PMOS performance by optimizing within wafer (WiW) uniformity for lateral growth and Boron concentration. The new process reduced growth related defect issues on large die products and excess abnormal growth defects to improve yield and reliability of latest semiconductor chips.

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2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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