神经形态硬件中记忆器件的线性优化

Jingyan Fu, Zhiheng Liao, Na Gong, Jinhui Wang
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引用次数: 4

摘要

记忆电阻器作为神经形态计算的硬件解决方案具有优势,但其非线性特性使得权重更新困难,降低了神经网络的精度。本文提出了一种分段线性(PL)方法,通过沿分段线计算权值更新参数来减轻忆阻器的非线性影响,从而减小了权值更新过程中的误差。这是一种简单而有效的非线性缓解方法,无需在每次更新时读取忆阻器的电流电导,从而避免了复杂的外围电路。研究了2段、3段和4段三种分割点选择策略下的分割点识别方法,结果表明:在不同非线性下,分割点识别方法对MNIST手写数字的识别准确率为87.87% ~ 95.05%,而未分割点识别方法的识别准确率为10.77% ~ 73.18%。最后得出结论:在PL方法中,节段越多,由突触器件非线性引起的权重偏差越小。
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Linear Optimization for Memristive Device in Neuromorphic Hardware
Memristors offer advantages as a hardware solution for neuromorphic computing, however, their nonlinear property makes the weight update difficult and reduces the accuracy of a neural network. A piecewise linear (PL) method is proposed in this paper to mitigate the nonlinear effect of memristors by calculating the weight update parameters along a piecewise line, which reduces errors in the weight update process. It is a simple but efficient method for the nonlinearity mitigation without reading the current conductance of the memristor in each updating, thereby avoiding complex peripheral circuits. The PL methods with respectively with 2-segment, 3-segment, and 4-segment models in two split points selection strategies are investigated, and the results show that under different nonlinearity, the PL method improves the recognition accuracy of MNIST handwriting digits to 87.87%-95.05%, as compared to 10.77%-73.18% of the cases without PL method. Finally, it concludes that the more segments in PL methods, the less weight deviation caused by the non-linearity of the synapse device.
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