基于32nm CMOS的2.8GHz 128入口× 152b 3读2写多精度浮点寄存器文件和shuffle

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243818

S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar

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引用次数: 8

摘要

在1.05V, 32nm CMOS上，制作了一个128位× 152b 3读2写多精度浮点寄存器文件/shuffle，测量工作频率为2.8GHz。单精度(24b-尾数)，2路12b或4路6b减小尾数精度模式，确定跟踪位，模式相关门控，使用1R/1W电池的面积高效窗口，以及超低电压读/写电路，使350mV-1.2V宽动态电压范围具有测量的峰值能量效率751GOPS/W在400mV, 4路6b模式(比1.05V单精度模式高22.3倍)和19%的面积比单精度3R/2W实现。

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A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS

A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.

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2012 Symposium on VLSI Circuits (VLSIC)

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