10mhz bw50fj /conv。采用基于优化设计方法的高阶单运放积分器的连续时间ΔΣ调制器

Kazuo Matsukawa, Koji Obata, Y. Mitani, S. Dosho
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引用次数: 36

摘要

本文提出了一种新的功率和面积有效的电路结构,以及这种结构的优化设计方法。制造了两种类型的环滤波器,一种是用于移动电视调谐器(调制器a)的单运放三阶积分器,另一种是用于宽带移动接收器的四阶(调制器B)。调制器A和调制器B分别采用65 nm和40 nm的CMOS工艺制造。结果表明,新型滤波器配合高效的优化工具是开发高效ΔΣ的有力途径。
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A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method
This paper proposes a new power and area efficient circuit configurations, and also an optimization design method for such configurations. Two types of loopfilters are fabricated, one is a third-order integrator with single opamp for mobile TV-tuners (Modulator A) and the other is a fourth-order (Modulator B) for wide-band mobile receivers. Modulator A and Modulator B are fabricated in 65 nm and 40 nm CMOS processes, respectively. Results show that the new filter with an efficient optimization tool is a very powerful way to develop high efficient ΔΣ.
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