Design of a CMOS Low-Power Limiting Amplifier with RSSI Integrated Circuit for Low-Frequency Wake-Up Receivers

This paper presents the circuit level design of a CMOS low power limiting amplifier with received signal strength indicator (RSSI) for low frequency application. The design utilizes a five-stage cascade amplifier with PMOS double diode-connected load for the limiting amplifier and a successive detection log amp for the RSSI structure. DC feedback technique is employed to suppress the DC offset at the output. The proposed circuit is laid out in $\pmb{0.13 \ \mu}\mathbf{m}$ CMOS technology, then extracted and simulated. It occupies a minimal active area of 0.0084 mm2and is able to operate within a frequency range of 17 kHz to 166 kHz with an RSSI error less than 2dB, while consumes only $\pmb{1.96\mu}\mathbf{A}$ current. It also achieves the −3dB input sensitivity of less than $\pmb{12\mu}\mathbf{V}_{\mathbf{rms}}$ for a typical dynamic range of 81.7 dB, and a maximum settling time of $\pmb{236}\ \pmb{\mu}\mathbf{s}$. Compared with best performer circuits, our design has the lowest power consumption while other performance aspects are comparable or better.