采用模拟FE的25gb /s 2.2 w光模块,可承受电源噪声和冗余数据格式转换,采用65nm CMOS

T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura
{"title":"采用模拟FE的25gb /s 2.2 w光模块,可承受电源噪声和冗余数据格式转换,采用65nm CMOS","authors":"T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura","doi":"10.1109/VLSIC.2012.6243812","DOIUrl":null,"url":null,"abstract":"A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS\",\"authors\":\"T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura\",\"doi\":\"10.1109/VLSIC.2012.6243812\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243812\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19

摘要

在65纳米CMOS中集成模拟有限元和数据格式转换,开发了一种用于光背板的单片收发器。10×6.25Gb/s的电信号转换为4×25Gb/s的光信号,具有25%的冗余,以提高对可能的LD故障的弹性。为了减轻由于电源变化引起的光链路退化,提出了一种带噪声消除器和全差分LDD的TIA。噪声消除器减少了98%的电源变化。总功耗仅为2.2W。
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A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS
A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.
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