Gate Voltage Oscillation Model and Suppression Method for Enhancement‐Mode GaN Devices in Half‐Bridge Circuits

This article analyzes the issue of gate voltage oscillations in AlGaN/GaN high electron mobility transistors based on the half‐bridge circuit. With the influence of the parasitic parameters, the variation of high drain‐source voltage (Vds) can affect the gate‐source voltage (Vgs), thus resulting in serious gate voltage oscillations, which may cause over‐voltage, false turn‐on/off, and even gate breakdown. A large‐signal model is proposed to study this oscillations phenomenon. The oscillation model of Vgs is proposed as a step response of Vds. Based on the model, the influence of Vds and circuit parameters on Vgs are investigated, and guidelines to suppress the oscillation are given. Reducing the gate and power loop inductance in PCB wiring and increasing the gate resistance of inactive switch can significantly suppress the oscillation. Finally, the model is verified by both simulation results and experimental results.