Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor

A surface potential based compact model for a long channel MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type Double Gate Negative Capacitance transistor (DG-NCFET) is presented in this paper. We propose an explicit continuous formulation of the drain current in terms of an intermediate parameter which is solved using a compact modeling approach. The proposed model captures a wide range of ferroelectric material parameter variations of a DG-NCFET in the non-hysteretic regime of operation. We implement our compact model in Verilog-A code and validate extensively with TCAD simulation results. We test the transient capability of the proposed model by simulating NCFET based 15-stage ring oscillator in a commercial circuit simulator.