Effect of Gate-lap and Oxide Material at 10-nm FinFET Device Performance

FinFETs have displayed superior electrical behavior as the promising substitute to the planar devices with improved electrostatic control, though FinFETs have been encountered with key obstacles of device scaling for better performance. In this research work, a FinFET structure has been simulated at 10-nm technology node. The electrical performance of the device has been investigated at various gatelap lengths and with utilizing high-k gate insulating material in the device structure for understanding their influence on the device performance. Low subthreshold$\sim 76.33$ mV/decade is obtained at gate-lap distance 0.5 nm. There have been obtained improvements in the ON to OFF current Ratio (ION/IOFF), Subthreshold swing (SS), and Drain Induced Barrier Lowering (DIBL) when the gate-lap length is varied. The results showed significant role of gate-lap length variation in the device parametrs. These research results are useful in guiding for scaling and design improvements of multi-gate device structures.