A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS

High-performance computing (HPC) systems demand aggressive scaling of memory and I/O to achieve multiple terabits/sec of bandwidth. Minimizing I/O cost, area and power are crucial to achieving a practically realizable system with such large bandwidth. To meet these needs, we developed a low-power dense 64-lane I/O system with per-port aggregate bandwidth up to 1Tb/s and 2.6pJ/bit power efficiency. We developed a high-density connector and cable, attached to the top side of the package that enables this high interconnect density. A lane-failover mechanism provides design robustness for fault-tolerance. To further optimize power efficiency, the lane data rate scales from 2 to 16Gb/s with non-linear power efficiency of 0.8 to 2.6pJ/bit, providing scalable aggregate bandwidth of 0.128 to 1Tb/s. Highly power scalable circuits such as CMOS clocking and reconfigurable current-mode (CM) or voltage-mode (VM) TX driver enable the 8× bandwidth and 3× power efficiency scalability with aggressive supply voltage scaling (0.6 to 1.08V).