Circuit level technique for mitigating effects of NBTI for wide fan-in domino logic circuits using supply voltage tuning

Transistor ageing has been a major problem as far as nanometre technology is concerned which leads to performance degradation and reliability issues. Ageing in pMOS transistor takes place due to Negative bias temperature instability (NBTI) which is a major threat in reliability as Iscale down the transistor geometries aggressively in our quest for low power and high performance. Overcoming ageing effect requires additional power expense, which in turn aggravates the power and heating problem. I propose an adaptive supply voltage (ASV) scheme as an arguably power efficient approach for variation resilience since it attempts to allocate power resources only where the negative effect of ageing is strong. Upon implementing the proposed approach on a host of domino logic circuits which include Current comparison domino (CCD) Ihave mitigated the rise in delay problem by suitably allocating a supply voltage so that the delay specifications are continuously met even after a lifespan of 10 years of operation at the expense of very low power headroom. Simulations have been performed using the BSIM4v4.7 model & 32 nm predictive technology model in SILVACO EDA tool at a frequency of 2 GHz and nominal supply voltage of 0.9V. The proposed approach has been implemented on 32 bit & 64 bit OR gates and also on 32 bit comparator and the results have been noteworthy.