A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques

This work proposes bit-line (BL) swing expansion schemes (BL-EXPD), which minimize the product (A*VDDmin) of SRAM cell area (A) and the minimum operation voltage (VDDmin) to the best of our knowledge. The key-enablers to minimize A*VDDmin are: L-shaped 7T cell (L7T) and BL-EXPD. The L7T features: (1) an area efficient cell layout, (2) a read-disturb free decoupled 1T read port (RP), and (3) a half-select disturb free write back scheme[1]. The BL-EXPD enables a 9× larger read-BL (RBL) swing at the 6σ point than that in our previously proposed Z8T[2] and allows single BL sensing to reduce cell area. A fabricated 65nm 256-row BL 32Kb L7T SRAM achieved a 260mV VDDmin. As a result, its A*VDDmin is ~50% lower than for Z8T and conventional 8T SRAM cells [3,4].