干涉原位III/V半导体干蚀刻深度控制±0.8 nm的最佳精度使用四倍游标尺度测量

G. Sombrio, Emerson Oliveira, J. Strassner, Christoph Doering, H. Fouckhardt
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引用次数: 3

摘要

半导体多层和器件制造是电子和光电子领域的一项复杂任务。层干蚀刻是实现特定横向器件设计的工艺步骤之一。如果需要高精度的蚀刻深度,则需要对蚀刻深度进行现场实时监测。非破坏性光学技术是首选的方法。利用反射各向异性光谱设备对反应离子蚀刻过程中III/V半导体样品的精确蚀刻深度进行了现场实时监测。为了这个目的,时间法布里-珀罗振荡由于蚀刻相关的收缩厚度的最上层已被利用。之前,我们已经报道了±16.0 nm的蚀刻深度分辨率。通过使用四倍游标尺度测量和评估方案,现在我们甚至将现场实时蚀刻深度分辨率提高了20倍,即名义上降至±0.8 nm。
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Interferometric in-situ III/V semiconductor dry-etch depth-control with ±0.8 nm best accuracy using a quadruple-Vernier-scale measurement
Semiconductor multilayer and device fabrication is a complex task in electronics and opto-electronics. Layer dry etching is one of the process steps to achieve a specific lateral device design. In situ and real-time monitoring of etch depth will be necessary if high precision in etch depth is required. Nondestructive optical techniques are the methods of choice. Reflectance anisotropy spectroscopy equipment has been used to monitor the accurate etch depth during reactive ion etching of III/V semiconductor samples in situ and real time. For this purpose, temporal Fabry–Perot oscillations due to the etch-related shrinking thickness of the uppermost layer have been exploited. Earlier, we have already reported an etch-depth resolution of ±16.0 nm. By the use of a quadruple-Vernier-scale measurement and an evaluation protocol, now we even improve the in situ real-time etch-depth resolution by a factor of 20, i.e., nominally down to ±0.8 nm.
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