{"title":"基于代理建模技术的平面电感器多目标混合整数设计优化","authors":"S. Koziel, P. Kurgan, John W. Handler","doi":"10.1109/MWSYM.2017.8058950","DOIUrl":null,"url":null,"abstract":"In this paper, we discuss multi-objective design optimization of planar inductors using surrogate modeling techniques. The goal is to identify the best possible trade-offs between the quality factor of the inductor and its size while maintaining a required value of the inductance at a given operating frequency. The design problem is formulated as a mixed-integer task involving geometry parameters as well as the number of inductor windings. The initial Pareto front is found by optimizing a data-driven surrogate of the structure at hand, further refined by means of response correction techniques. Our considerations are illustrated using a 3.5-nH spiral inductor implemented in 65-nm CMOS technology.","PeriodicalId":6481,"journal":{"name":"2017 IEEE MTT-S International Microwave Symposium (IMS)","volume":"12 1","pages":"1632-1634"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Multi-objective mixed-integer design optimization of planar inductors using surrogate modeling techniques\",\"authors\":\"S. Koziel, P. Kurgan, John W. Handler\",\"doi\":\"10.1109/MWSYM.2017.8058950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we discuss multi-objective design optimization of planar inductors using surrogate modeling techniques. The goal is to identify the best possible trade-offs between the quality factor of the inductor and its size while maintaining a required value of the inductance at a given operating frequency. The design problem is formulated as a mixed-integer task involving geometry parameters as well as the number of inductor windings. The initial Pareto front is found by optimizing a data-driven surrogate of the structure at hand, further refined by means of response correction techniques. Our considerations are illustrated using a 3.5-nH spiral inductor implemented in 65-nm CMOS technology.\",\"PeriodicalId\":6481,\"journal\":{\"name\":\"2017 IEEE MTT-S International Microwave Symposium (IMS)\",\"volume\":\"12 1\",\"pages\":\"1632-1634\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE MTT-S International Microwave Symposium (IMS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSYM.2017.8058950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE MTT-S International Microwave Symposium (IMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2017.8058950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multi-objective mixed-integer design optimization of planar inductors using surrogate modeling techniques
In this paper, we discuss multi-objective design optimization of planar inductors using surrogate modeling techniques. The goal is to identify the best possible trade-offs between the quality factor of the inductor and its size while maintaining a required value of the inductance at a given operating frequency. The design problem is formulated as a mixed-integer task involving geometry parameters as well as the number of inductor windings. The initial Pareto front is found by optimizing a data-driven surrogate of the structure at hand, further refined by means of response correction techniques. Our considerations are illustrated using a 3.5-nH spiral inductor implemented in 65-nm CMOS technology.