一个8 ppm, 45 pJ/bit的UWB发射机，减少了PA元件的数量

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243777

V. Majidzadeh, A. Schmid, Y. Leblebici, J. Rabaey

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引用次数: 9

摘要

提出了一种利用有限脉冲响应合成提高余弦脉冲的脉冲超宽带发射机(Tx)。为了将功率放大器的元件数量减少一半，提出了对称脉冲组合技术。新型全数字延迟锁环(AD-DLL)作为8阵列脉冲位置调制器(PPM)，用于Tx的主动占空比。该芯片采用90nm CMOS技术制造，从1 V电源消耗540 μW，输出功率为-26 dBm，能量效率为45 pJ/bit。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements

A pulsed UWB transmitter (Tx) using finite impulse response synthesis of the raised-cosine pulse is presented. Symmetric pulse combining technique is proposed to reduce the number of power amplifier elements by half. A novel all-digital delay locked loop (AD-DLL) serves as an 8-array pulse position modulator (PPM) for aggressive duty-cycling of the Tx. The chip is fabricated with 90nm CMOS technology and consumes 540 μW from 1 V power supply resulting in 45 pJ/bit energy efficiency with -26 dBm of output power.

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2012 Symposium on VLSI Circuits (VLSIC)

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