采用设计强化辐射(RHBD)技术设计组合和顺序标准电池

H. K. Dwivedi, Shuvendu Nandi, Shweta Lahariya, Sangeeta Nakhate
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引用次数: 1

摘要

在Cadence Virtuoso中使用SCL PDK,对基于0.18μmCMOS技术的组合和顺序标准细胞的传统和RHBD技术进行了比较。在太空中,放射性粒子(质子、中子、α)和重离子对集成电路(IC)构成最大的威胁。随着特征尺寸的不断减小和电源电压的不断降低,引起的单事件瞬变(set)问题已成为深亚微米技术(DSM)中组合和顺序数字电路的主要问题。所研究的基于C元的单元有逆变器、非与门、缓冲器和d触发器。这些单元的示意图和布局是使用Cadence Virtuoso工具开发的。采用RHBD方法设计的电路对单事件效应(SEE)的容忍度更高,具有更好的抗噪性和更低的静态功耗。与DCVSL方法相比,该方法的平均功率降低了94%,延迟降低了85%。
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Combinational and sequential standard cell design using Radiation Hardened By Design (RHBD) Technique
The work in this paper centres around comparison amongst conventional and RHBD technique based combinational and sequential standard cells in 0.18μmCMOS technology using SCL PDK in Cadence Virtuoso. In space radioactive particles (proton, neutrons, $\alpha$) and heavy ions makes the biggest threat to Integrated Circuits (IC). With continuously decreasing feature size and lowering of the supply voltage, causes Single Event Transients (SETs) which is becoming a major problem for both combinational and sequential digital circuits in the Deep Submicron technology (DSM). The proposed C- element based cells investigated are Inverter, NAND gate, Buffer and D-Flip Flop. Schematic and layout of these cells are developed using Cadence Virtuoso tool. Circuits which are designed with the RHBD approaches are more tolerant to Single Event Effects (SEE), have better noise immunity and less static power consumption. The reduction in the average power in proposed style is 94% and the delay reduction is 85% as compared to DCVSL methodology.
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