一种新型10位1.2GS/s混合数模转换器,功耗8.4mW

A. Ahmadi, Hossein Ghasemian, E. Abiri, R. Ghasemi
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引用次数: 1

摘要

本文提出了一种新型的10位1.2 GS/s混合数模转换器(DAC)。在这项工作中,在单位电流源旁边的电阻梯被用来实现高值位。使用电阻阶梯来缩放电流源,可以显著减少电流源的数量。此外,用于分段结构的复杂解码器电路被具有更少晶体管的简单数字逻辑所取代。在65 nm CMOS技术下的仿真结果表明,所提出的DAC功耗仅为8.4 mW,电源为1.2 V,与最近的工作相比,这是一个改进。仿真结果表明,INL和DNL分别小于0.25和0.12 LSB。此外,在整个600 MHz奈奎斯特带宽中获得了超过74 dB的SFDR。
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A Novel 10-bit 1.2GS/s Hybrid Digital to Analog Converter with 8.4mW Power Consumption
In this paper, a novel 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) is presented. In this work, a resistor ladder beside the unit current sources is employed to implement the higher value bits. Using a resistor ladder for scaling the current sources causes to decrease the number of current sources impressively. In addition, the complicated decoder circuits used in segmented structures are replaced by simple digital logics with fewer transistors. simulation results in 65 nm CMOS technology demonstrate that the proposed DAC consumes only 8.4 mW power with a 1.2 V power supply, which is an improvement in comparison with recent works. Moreover, simulation results show that the INL and DNL are less than 0.25 and 0.12 LSB, respectively. Also, more than 74 dB SFDR is obtained in the entire 600 MHz Nyquist bandwidth.
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