{"title":"一个0.41µA待机泄漏32Kb嵌入式SRAM,采用28nm HKMG CMOS全数字电流比较器,具有低压恢复待机功能","authors":"N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki","doi":"10.1109/VLSIC.2012.6243788","DOIUrl":null,"url":null,"abstract":"A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"106 1","pages":"58-59"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS\",\"authors\":\"N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki\",\"doi\":\"10.1109/VLSIC.2012.6243788\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"106 1\",\"pages\":\"58-59\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243788\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243788","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.