Hybrid parallelization of the black hole algorithm for systems on chip

Black Hole (BH) is a bioinspired metaheuristic algorithm based on the theory of relativity in which a sufficiently compact mass can deform the space-time to form a black hole, where no particles or electromagnetic radiation can escape from it. Thus, such an approach is based on the concept of a population of individuals (stars) representing solutions for a given computational problem to be optimized. In the literature, such an approach has been used to solve clustering problems, among others, since it is parameter-free and simple to implement. In this article, due to such characteristics, a hybrid solution, in software/hardware, of parallelization of the BH algorithm is proposed, aiming at accelerating its processing in hardware through a methodology that allows any user, even non-expert, implement hardware accelerators, for optimization problems, among others, through a high level tool. A System on Chip (SoC) platform was used for this implementation, containing a Zynq chip from Xilinx, which has two ARM cores and an FPGA. The BH Algorithm was implemented in software first and then in hardware for runtime comparison purposes to validate this approach. Also, in this paper, simpler and more popular optimization algorithms, such as Particle Swarm Optimization (PSO), Gravitational Search (GSA), and Big Bang – Big Crunch (BB-BC), along with simpler datasets, were used for comparison purposes, due to its ease of implementation and to keep a fairer comparison with BH as realized in other works in the literature. Therefore, the results obtained were satisfactory in terms of execution time and quality, with an average speedup of 25 times compared to the same implementation in software. In the future, it is intended to use this procedure to implement more recent clustering and optimization algorithms with larger datasets as well.