Stress evaluations in micro bump structures of FCBGA

System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump.