基于FPGA的TDC使用Virtex-4 ISERDES块

IEEE Nuclear Science Symposuim & Medical Imaging Conference Pub Date : 2010-12-01 DOI:10.1109/NSSMIC.2010.5874005

G. Hegyesi, G. Kalinka, J. Molnár, F. Nagy, J. Imrek, I. Valastyán, Z. Szabó

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引用次数: 2

摘要

我们报告了基于Virtex-4 ISERDES块的交错TDC架构的实现。在分相安排中，每个输入通道使用多个ISERDES块。该架构具有中等分辨率(在本实现中为312 ps)，对PVT变化不敏感，只需要有限的FPGA资源，因此适合高通道计数。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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FPGA based TDC using Virtex-4 ISERDES blocks

We report on the implementation of an interleaving TDC architecture based on Virtex-4 ISERDES blocks. Multiple ISERDES blocks are used for each input channel in a split-phase arrangement. The architecture has moderate resolution (312 ps in this implementation), it is not sensitive to PVT variations, requires only limited FPGA resources, and thus suitable for high channel counts.

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IEEE Nuclear Science Symposuim & Medical Imaging Conference

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