提高安全性的时域顺序锁定

Kyle Juretus, I. Savidis
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引用次数: 14

摘要

本文利用集成电路的状态空间来提高集成电路的安全性,以抵御各种威胁,包括知识产权盗窃、IC伪造和IC生产过剩。隐藏状态转换、依赖于状态的键和基于时间的转换被实现为对抗探测式攻击(如SAT攻击)的一种手段。SPICE仿真在修改后的状态机上进行,以表征在电路中实现这三种技术的开销。实现基于时间的转换使电路的面积增加了68.42%,功率增加了43.17%,并且不影响电路延迟。然而,增加电路尺寸可以显著减少状态空间加密的开销。例如,在s15850 ISCAS89基准电路中加密两个寄存器会导致0.026%的面积开销,这是一种低开销的保护顺序逻辑的方法。
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Time Domain Sequential Locking for Increased Security
In this paper, the state space of an integrated circuit (IC) is used to increase the security of an IC against a variety of threats including intellectual property theft, IC counterfeiting, and IC overproduction. Hidden state transitions, state dependent keys, and temporal based transitions are implemented as a means to combat probing style attacks, such as the SAT attack. SPICE simulations are performed on modified state machines to characterize the overhead of implementing the three techniques in a circuit. Implementing temporal based transitions increases the area of the circuit by 68.42%, the power by 43.17%, and did not impact circuit delay. However, increasing the circuit size significantly reduces the overhead of state space encryption. For example, encrypting two registers in the s15850 ISCAS89 benchmark circuit resulted in an area overhead of 0.026%, presenting a low overhead means of securing sequential logic.
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