N. Ketteniss, B. Reuters, B. Hollander, H. Hahn, H. Kalisch, A. Vescan
{"title":"第四季氮化物增强模式HFET, 260ms /mm,阈值电压+0.5 V","authors":"N. Ketteniss, B. Reuters, B. Hollander, H. Hahn, H. Kalisch, A. Vescan","doi":"10.1109/DRC.2012.6257030","DOIUrl":null,"url":null,"abstract":"A new approach for the heterostructure design following the idea to reduce the interface charge itself by applying a quaternary barrier layer with rather low polarization is demonstrated. The enhancement mode (e-mode) heterostructure field effect transistors (HFET) is consist of a GaN buffer and a quarternary barrier layers, whose composition and thickness are chosen carefully to result in an e-mode device. The devices is passivated with 120 nm SiN by plasma enhanced CVD. An increase in gate and drain leakage can be observed and finds its origin in surface or interface conductivity of the not fully optimized SiN. Nevertheless, for all devices the extrinsic transconductance has increased due to further carrier concentration enhancement in the access region by the passivation, and the best performance is achieved with maximum extrinsic transconductance of 260 mS/mm, which is among the highest reported for a 1 11m gate length e-mode HFET.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"17 1","pages":"161-162"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Quaternary nitride enhancement mode HFET with 260 mS/mm and a threshold voltage of +0.5 V\",\"authors\":\"N. Ketteniss, B. Reuters, B. Hollander, H. Hahn, H. Kalisch, A. Vescan\",\"doi\":\"10.1109/DRC.2012.6257030\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new approach for the heterostructure design following the idea to reduce the interface charge itself by applying a quaternary barrier layer with rather low polarization is demonstrated. The enhancement mode (e-mode) heterostructure field effect transistors (HFET) is consist of a GaN buffer and a quarternary barrier layers, whose composition and thickness are chosen carefully to result in an e-mode device. The devices is passivated with 120 nm SiN by plasma enhanced CVD. An increase in gate and drain leakage can be observed and finds its origin in surface or interface conductivity of the not fully optimized SiN. Nevertheless, for all devices the extrinsic transconductance has increased due to further carrier concentration enhancement in the access region by the passivation, and the best performance is achieved with maximum extrinsic transconductance of 260 mS/mm, which is among the highest reported for a 1 11m gate length e-mode HFET.\",\"PeriodicalId\":6808,\"journal\":{\"name\":\"70th Device Research Conference\",\"volume\":\"17 1\",\"pages\":\"161-162\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"70th Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2012.6257030\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"70th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2012.6257030","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Quaternary nitride enhancement mode HFET with 260 mS/mm and a threshold voltage of +0.5 V
A new approach for the heterostructure design following the idea to reduce the interface charge itself by applying a quaternary barrier layer with rather low polarization is demonstrated. The enhancement mode (e-mode) heterostructure field effect transistors (HFET) is consist of a GaN buffer and a quarternary barrier layers, whose composition and thickness are chosen carefully to result in an e-mode device. The devices is passivated with 120 nm SiN by plasma enhanced CVD. An increase in gate and drain leakage can be observed and finds its origin in surface or interface conductivity of the not fully optimized SiN. Nevertheless, for all devices the extrinsic transconductance has increased due to further carrier concentration enhancement in the access region by the passivation, and the best performance is achieved with maximum extrinsic transconductance of 260 mS/mm, which is among the highest reported for a 1 11m gate length e-mode HFET.