Model-based framework for networks-on-chip design space exploration

With increasing density on circuits, more cores are integrated. Networks-on-chip (NoCs) is emerged as a solution for interconnect. Many router architectures, NoC topologies and routing algorithms are developed to improve NoC design. This brings a large design space to explore. The exploration requires various models and tools to evaluate NoCs. So this paper proposes a model-based framework that can integrate different evaluation together. Each NoC design is processed as one model using Eclipse Modelling Framework (EMF). Models can be used in code generation to generate different evaluation models, including ORION, SystemC and LISNoC Verilog description. An execution is further developed to compile, execute and synthesize models. The framework is experimented with both a real multi-media application and random traffic tests. Various aspects of evaluation are reported, including latency, throughoutput, buffer utilization, area, power and so on.