A Clock Jitter Tolerant ΣΔ Modulator Employing a Hybrid Loop Filter in CMOS 40NM Technology

A Sigma-Delta Modulator (ΣΔ) that employs a hybrid loop filter to reduce its sensitivity to clock jitter is proposed. Part of the loop filter is implemented in the digital domain. The clock jitter effects are significantly reduced without changing the loop gain properties. The ΣΔ Modulator is implemented in TSMC 40 nm CMOS technology and occupies a 0.06 mm2. The solution consumes 6.9mW and operates at a clock rate of 500 MS/s. In the presence of 20psrms clock jitter (peak to peak jitter of almost 215 ps) and bandwidth of 10 MHz, the measured peak signal-to-noise-ratio (SNR) and peak signal-to-noise+distortion ratio (SNDR) are 65 dB, and 64 dB, respectively.